14–10
Altera Corporation
Stratix GX Device Handbook, Volume 2
July 2005
Using TriMatrix Memory
M512 blocks support serializer and deserializer (SERDES) applications.
By using the mixed-width support in combination with double data rate
(DDR) I/O standards, the block can function as a SERDES to support low-
speed serial I/O standards using global or regional clocks.
f
For more information on Stratix device I/O structure see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1.
For more information on Stratix GX device I/O structure see the
Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
In simple dual-port mode, the M512 and M4K blocks have one write
enable and one read enable signal. The M512 does not support a clear port
on the rden register. On the M4K block, asserting the clear port of the
rden
register drives rden high, which allows the read operation to occur.
When the read enable is deactivated, the current data is retained at the
output ports. If the read enable is activated during a write operation with
the same address location selected, the simple dual-port RAM output is
either unknown or can be set to output the old data stored at the memory
128
× 32
vvv
v
512
× 9
vv
v
256
× 18
vv
v
128
× 36
vv
v
Table 14–9. M-RAM Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port
Write Port
64K
× 932K × 18
16K
× 36
8K
× 72
4K
× 144
64K
× 9
vvvv
32K
× 18
vvvv
16K
× 36
vvvv
8K
× 72
vvvv
4K
× 144
v
Table 14–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Read Port
Write Port
4K
× 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
