- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4339 > EP1SGX25CF672C5 (Altera)IC STRATIX GX FPGA 25KLE 672FBGA PDF資料下載
參數(shù)資料
| 型號： | EP1SGX25CF672C5 |
| 廠商： | Altera |
| 文件頁數(shù)： | 1203/1456頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX GX FPGA 25KLE 672FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 20 |
| 系列： | Stratix® GX |
| LAB/CLB數(shù)： | 2566 |
| 邏輯元件/單元數(shù)： | 25660 |
| RAM 位總計： | 1944576 |
| 輸入/輸出數(shù)： | 455 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 672-BBGA |
| 供應商設備封裝： | 672-BGA（27x27） |
6–14
Altera Corporation
Stratix GX Device Handbook, Volume 2
June 2006
GIGE Mode Transmitter Architecture
Figure 6–14. Control Code Detection
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer is located at the FPGA logic
array interface in the receiver block and is four words deep. This FIFO
buffer compensates for the phase difference between the clock in the
FPGA and the operating clocks in the transceiver block.
In GIGE mode, the write port is clocked by the refclk from the
transmitter phase-locked loop (PLL). The read clock is clocked by
CORECLK
(output from the transmitter PLL). The receiver phase
compensation FIFO buffer can only account for phase differences and
must be derived from the recovered clock of its associated channel.
The receiver phase compensation FIFO buffer is always used, and you
cannot bypass it.
GIGE Mode
Transmitter
Architecture
Figure 6–15 shows the digital components of the Stratix GX transmitter
that are active in GIGE mode.
clock
rx_out[7:0]
rx_ctrldetect
83
78
BC
07
0F
00
BF
3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
Code Group
相關PDF資料 |
PDF描述 |
|---|---|
| 180-015-173L020 | CONN DB15 MALE HD CRIMP NICKEL |
| ACC49DRTI-S93 | CONN EDGECARD 98POS DIP .100 SLD |
| A54SX16-1CQ256 | IC FPGA SX 24K GATES 256-CQFP |
| EP3SL110F780C3N | IC STRATIX III L 110K 780-FBGA |
| FMC19DRYI-S734 | CONN EDGECARD 38POS DIP .100 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1SGX25CF672C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25CF672C6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25CF672C6N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25CF672C7 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25CF672C7N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復。