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參數(shù)資料
| 型號： | EP1SGX25CF672C7N |
| 廠商： | Altera |
| 文件頁數(shù)： | 581/1456頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX GX FPGA 25KLE 672FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 20 |
| 系列： | Stratix® GX |
| LAB/CLB數(shù)： | 2566 |
| 邏輯元件/單元數(shù)： | 25660 |
| RAM 位總計： | 1944576 |
| 輸入/輸出數(shù)： | 455 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 672-BBGA |
| 供應商設備封裝： | 672-BGA（27x27） |
Altera Corporation
2–1
June 2006
2. Stratix GX Transceivers
Transceiver
Blocks
Stratix GX devices incorporate dedicated embedded circuitry on the
right side of the device, which contains up to 20 high-speed 3.1875-Gbps
serial transceiver channels. Each Stratix GX transceiver block contains
four full-duplex channels and supporting logic to transmit and receive
high-speed serial data streams. The transceiver block uses the channels to
deliver bidirectional point-to-point data transmissions with up to
3.1875 Gbps of data transition per channel.
There are up to 20 transceiver channels available on a single Stratix GX
device. Table 2–1 shows the number of transceiver channels available on
each Stratix GX device.
Figure 2–1 shows the elements of the transceiver block, including the four
channels, supporting logic, and I/O buffers. Each transceiver channel
consists of a receiver and transmitter. The supporting logic contains a
transmitter PLL to generate a high-speed clock used by the four
transmitters. The receiver PLL within each transceiver channel generates
the receiver reference clocks. The supporting logic also contains state
machines to manage rate matching for XAUI and GIGE applications, in
addition to channel bonding for XAUI applications.
Table 2–1. Stratix GX Transceiver Channels
Device
Number of Transceiver Channels
EP1SGX10C
4
EP1SGX10D
8
EP1SGX25C
4
EP1SGX25D
8
EP1SGX25F
16
EP1SGX40D
8
EP1SGX40G
20
SGX51002-1.1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1SGX25CF672I6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25CF672I6N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25D | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:StratixGX FPGA Family |
| EP1SGX25DF1020C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 607 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25DF1020C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 2566 LABs 607 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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