參數(shù)資料
型號: EP20K1500CF1020C8
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 42/114頁
文件大小: 1623K
代理商: EP20K1500CF1020C8
Altera Corporation
33
APEX 20K Programmable Logic Device Family Data Sheet
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers. Figure 21 shows
the ESB in input/output clock mode.
Figure 21. ESB in Input/Output Clock Mode
Notes:
(1)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2)
APEX 20KE devices have four dedicated clocks.
Dedicated Clocks
2 or 4
4
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
128
× 16
256
× 8
512
× 4
1,024
× 2
2,048
× 1
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
outclken
inclken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Dedicated Inputs &
Global Signals
to MegaLAB,
FastTrack &
Local
Interconnect
(2)
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