參數(shù)資料
型號: EP20K160EBI356-1ES
英文描述: 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-FlatPack
中文描述: FPGA的
文件頁數(shù): 52/114頁
文件大小: 1623K
代理商: EP20K160EBI356-1ES
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
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