參數(shù)資料
型號: EP20K200EFC484-2X
廠商: Altera
文件頁數(shù): 18/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 200K 484-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 60
系列: APEX-20K®
LAB/CLB數(shù): 832
邏輯元件/單元數(shù): 8320
RAM 位總計(jì): 106496
輸入/輸出數(shù): 376
門數(shù): 404000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FBGA(23x23)
其它名稱: 544-1098
114
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
SRAM configuration elements allow APEX 20K devices to be
reconfigured in-circuit by loading new configuration data into the
device. Real-time reconfiguration is performed by forcing the device
into command mode with a device pin, loading different
configuration data, reinitializing the device, and resuming user-
mode operation. In-field upgrades can be performed by distributing
new configuration files.
Configuration Schemes
The configuration data for an APEX 20K device can be loaded with
one of five configuration schemes (see Table 111), chosen on the basis
of the target application. An EPC2 or EPC16 configuration device,
intelligent controller, or the JTAG port can be used to control the
configuration of an APEX 20K device. When a configuration device
is used, the system can configure automatically at system power-up.
Multiple APEX 20K devices can be configured in any of five
configuration schemes by connecting the configuration enable (nCE)
and configuration enable output (nCEO) pins on each device.
f For more information on configuration, see Application Note 116
(Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices.)
Device Pin-Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library
for pin-out information
Table 111. Data Sources for Configuration
Configuration Scheme
Data Source
Configuration device
EPC1, EPC2, EPC16 configuration devices
Passive serial (PS)
MasterBlaster or ByteBlasterMV download cable or serial data source
Passive parallel asynchronous (PPA)
Parallel data source
Passive parallel synchronous (PPS)
Parallel data source
JTAG
MasterBlaster or ByteBlasterMV download cable or a microprocessor
with a Jam or JBC File
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EP20K200EFC484-2XN 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 376 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K200EFC484-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 376 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K200EFC484-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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EP20K200EFC672-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 376 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256