參數(shù)資料
型號: EP20K400EBC652-3N
廠商: Altera
文件頁數(shù): 43/117頁
文件大小: 0K
描述: IC APEX 20KE FPGA 400K 652-BGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 12
系列: APEX-20K®
LAB/CLB數(shù): 1664
邏輯元件/單元數(shù): 16640
RAM 位總計: 212992
輸入/輸出數(shù): 488
門數(shù): 1052000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 652-BGA
供應商設備封裝: 652-BGA(45x45)
Altera Corporation
31
APEX 20K Programmable Logic Device Family Data Sheet
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
ESB
to System Logic
Address Decoder
Port A
Port B
address_a[]
address_b[]
data_a[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
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