參數(shù)資料
型號: EP20K400EBI652-2X
廠商: Altera
文件頁數(shù): 45/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 400K 652-BGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 12
系列: APEX-20K®
LAB/CLB數(shù): 1664
邏輯元件/單元數(shù): 16640
RAM 位總計(jì): 212992
輸入/輸出數(shù): 488
門數(shù): 1052000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 652-BGA
供應(yīng)商設(shè)備封裝: 652-BGA(45x45)
Altera Corporation
33
APEX 20K Programmable Logic Device Family Data Sheet
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers. Figure 21 shows
the ESB in input/output clock mode.
Figure 21. ESB in Input/Output Clock Mode
Notes to Figure 21:
(1)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2)
APEX 20KE devices have four dedicated clocks.
Single-Port Mode
The APEX 20K ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See Figure 22.
Dedicated Clocks
2 or 4
4
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
128
× 16
256
× 8
512
× 4
1,024
× 2
2,048
× 1
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
outclken
inclken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Dedicated Inputs &
Global Signals
to MegaLAB,
FastTrack &
Local
Interconnect
(2)
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