please ref" /> 
<dfn id="4yilu"><pre id="4yilu"></pre></dfn>
    •         


    
    



    

    
  
    
    
    
    
    
      
    
    
  
    
  
  

    





    


    
 
 




 
 


    

    
    


    參數(shù)資料
    

    


    


    
型號：
EP20K400EFC672-1XN

    

    
廠商：
Altera

    

    
文件頁數(shù)：
80/117頁

    

    
文件大小：
0K

    

    
描述：
IC APEX 20KE FPGA 400K 672-FBGA

    

    
產(chǎn)品培訓模塊：
Three Reasons to Use FPGA's in Industrial Designs
    		

    

    
標準包裝：
40

    

    
系列：
APEX-20K®

    

    
LAB/CLB數(shù)：
1664
    		

    

    
邏輯元件/單元數(shù)：
16640
    		

    

    
RAM 位總計：
212992
    		

    

    
輸入/輸出數(shù)：
488
    		

    

    
門數(shù)：
1052000
    		

    

    
電源電壓：
1.71 V ~ 1.89 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
672-BBGA
    		

    

    
供應商設備封裝：
672-BGA（27x27）
    		

    

    

    

	
    
    
    

    
    
	
    Altera Corporation
    65
    APEX 20K Programmable Logic Device Family Data Sheet
    1
    For DC Operating Specifications on APEX 20KE I/O standards,
    please refer to Application Note 117 (Using Selectable I/O Standards
    in Altera Devices).
    Notes to Tables 27 through 30:
    (1)
    See the Operating Requirements for Altera Devices Data Sheet.
    (2)
    Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
    input currents less than 100 mA and periods shorter than 20 ns.
    (3)
    Numbers in parentheses are for industrial-temperature-range devices.
    (4)
    Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
    (5)
    Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the voltage
    shown in the following table based on input duty cycle for input currents less than 100 mA. The overshoot is
    dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
    Vin
    Max. Duty Cycle
    4.0V
    100% (DC)
    4.1
    90%
    4.2
    50%
    4.3
    30%
    4.4
    17%
    4.5
    10%
    (6)
    All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
    powered.
    (7)
    Typical values are for TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V or 3.3 V.
    (8)
    These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 24 on
    (9)
    Refer to Application Note 117 (Using Selectable I/O Standards in Altera Devices) for the VIH, VIL, VOH, VOL, and II
    parameters when VCCIO = 1.8 V.
    (10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
    Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
    SSTL-2, SSTL-3, and HSTL.
    (11) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
    (12) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
    as well as output pins.
    (13) This value is specified for normal device operation. The value may vary during power-up.
    (14) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
    (15) Capacitance is sample-tested only.
    Figure 33 shows the relationship between VCCIO and VCCINT for 3.3-V PCI
    compliance on APEX 20K devices.
    Table 30. APEX 20KE Device Capacitance
    Symbol
    Parameter
    Conditions
    Min
    Max
    Unit
    CIN
    Input capacitance
    VIN = 0 V, f = 1.0 MHz
    8
    pF
    CINCLK
    Input capacitance on
    dedicated clock pin
    VIN = 0 V, f = 1.0 MHz
    12
    pF
    COUT
    Output capacitance
    VOUT = 0 V, f = 1.0 MHz
    8
    pF
    
    
    
    
    
    


    


    

    相關PDF資料
    		

    PDF描述
    		

    
    

    
EP20K400EFC672-1X
IC APEX 20KE FPGA 400K 672-FBGA

    

    
EP2AGX125EF29I5
IC ARRIA II GX FPGA 125K 780FBGA

    

    
24LC08BHT-I/OT
IC EEPROM 8KBIT 400KHZ SOT23-5

    

    
AMM24DSAH
CONN EDGECARD 48POS R/A .156 SLD

    

    
EP2AGX125EF29C4
IC ARRIA II GX FPGA 125K 780FBGA

    

    

    

    


    


    

    相關代理商/技術參數(shù)
    		

    參數(shù)描述
    		

    
    

    
EP20K400EFC672-2
功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO

 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP20K400EFC672-2ES
 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA

    

    
EP20K400EFC672-2N
功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO

 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP20K400EFC672-2X
功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO

 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP20K400EFC672-3
功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macro 488 IOs

 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
    
    
    
	
    	
    
    
     
     
    發(fā)布緊急采購，3分鐘左右您將得到回復。
    
 
     
    

   	  
    
     

    
                    			    				      
    
                
    
                  
    
                    
                    
    
                      
    
                      
                      
    采購需求
      (若只采購一條型號，填寫一行即可)
    
                      
                      
    發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價
    
                      
                      
    發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價
    
                       
                        
    
                                
                                
    
                                    *型號
                                    *數(shù)量
                                    廠商
                                    批號
                                    封裝
                                  
    
                                    
                                
                                
    
                                    
                                        
    
                                            
                                            
                                        
    
                                        		
                                     
                                    
                                        
    
                                        		
                                    
                                        
    
                                        		
                                    
                                        
    
                                        		
                                    
                                        
    
                                        		
                                  
    
                                  
                                   
                                    
                            
    
                             
                             
							                            
    
                          添加更多采購
    
                      
    
                      
                      
    
                      
                      
    我的聯(lián)系方式
    
                     
                     
                       
    
                                
                                
                                
    
                                    
                                         *
                                    
                                    
                                  
    
                                  
                                  
    
                                    
                                         *
                                    
                                    
                                  
    
                                  
                                  
    
                                    
                                        
                                    
                                    
                                  
    
                                  
                                  
    
                                    
                                         *