參數(shù)資料
型號： EP20K400FC672-1
廠商： Altera
文件頁數(shù)： 59/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 400K 672-BGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 40
系列： APEX-20K®
LAB/CLB數(shù)： 1664
邏輯元件/單元數(shù)： 16640
RAM 位總計： 212992
輸入/輸出數(shù)： 502
門數(shù)： 1052000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BBGA
供應商設備封裝： 672-BGA（27x27）
46
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Under hot socketing conditions, APEX 20KE devices will not sustain any
damage, but the I/O pins will drive out.
MultiVolt I/O
Interface
The APEX device architecture supports the MultiVolt I/O interface
feature, which allows APEX devices in all packages to interface with
systems of different supply voltages. The devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The APEX 20K VCCINT pins must always be connected to a 2.5 V power
supply. With a 2.5-V VCCINT level, input pins are 2.5-V, 3.3-V, and 5.0-V
tolerant. The VCCIO pins can be connected to either a 2.5-V or 3.3-V power
supply, depending on the output requirements. When VCCIO pins are
connected to a 2.5-V power supply, the output levels are compatible with
2.5-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V
systems.
Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.
Notes to Table 12:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO.
(2)
When VCCIO = 3.3 V, an APEX 20K device can drive a 2.5-V device with 3.3-V
tolerant inputs.
Open-drain output pins on 5.0-V tolerant APEX 20K devices (with a pull-
up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that
require a VIH of 3.5 V. When the pin is inactive, the trace will be pulled up
to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state;
it will never drive high. The rise time is dependent on the value of the pull-
up resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor.
Table 12. 5.0-V Tolerant APEX 20K MultiVolt I/O Support
VCCIO (V)
Input Signals (V)
Output Signals (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
v
3.3
vv
vv
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相關代理商/技術參數(shù)
參數(shù)描述
EP20K400FC672-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400FC672-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400FC672-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macro 502 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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