- 您現在的位置：買賣IC網 > PDF目錄97925 > EP20K600EFC1020-3ES FPGA PDF資料下載
參數資料
| 型號： | EP20K600EFC1020-3ES |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數： | 46/114頁 |
| 文件大?。?/td> | 1623K |
| 代理商： | EP20K600EFC1020-3ES |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
Altera Corporation
37
APEX 20K Programmable Logic Device Family Data Sheet
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times of
ESBs. The large capacity of ESBs enables designers to implement complex
functions in one logic level without the routing delays associated with
linked LEs or distributed RAM blocks. Parameterized functions such as
LPM functions can take advantage of the ESB automatically. Further, the
Quartus II software can implement portions of a design with ESBs where
appropriate.
Programmable Speed/Power Control
APEX 20K ESBs offer a high-speed mode that supports very fast operation
on an ESB-by-ESB basis. When high speed is not required, this feature can
be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs
that run at low power incur a nominal timing delay adder. This
Turbo BitTM option is available for ESBs that implement product-term
logic or memory functions. An ESB that is not used will be powered down
so that it does not consume DC current.
Designers can program each ESB in the APEX 20K device for either
high-speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
I/O Structure
The APEX 20K IOE contains a bidirectional I/O buffer and a register that
can be used either as an input register for external data requiring fast setup
times, or as an output register for data requiring fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. For
fast bidirectional I/O timing, LE registers using local routing can improve
setup times and OE timing. The Quartus II software Compiler uses the
programmable inversion option to invert signals from the row and column
interconnect automatically where appropriate. Because the APEX 20K IOE
offers one output enable per pin, the Quartus II software Compiler can
emulate open-drain operation efficiently.
The APEX 20K IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-core register transfers, or core-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay.
相關PDF資料 |
PDF描述 |
|---|---|
| EP20K600EFC672-1ES | FPGA |
| EP20K600EFC672-2ES | FPGA |
| EP20K60EBC356-2ES | FPGA |
| EP20K60EBC356-3ES | FPGA |
| EP20K60EBI356-1ES | FPGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EP20K600EFC33-1 | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2432 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K600EFC33-1X | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2432 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K600EFC33-2 | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2432 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K600EFC33-2X | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2432 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K600EFC33-3 | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2432 Macro 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復。