參數(shù)資料
型號： EP2AGX125DF25C5
廠商： Altera
文件頁數(shù)： 14/90頁
文件大?。?/td> 0K
描述： IC ARRIA II GX FPGA 125K 572FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 5
系列： Arria II GX
LAB/CLB數(shù)： 4964
邏輯元件/單元數(shù)： 118143
RAM 位總計(jì)： 8315904
輸入/輸出數(shù)： 260
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 572-FBGA
供應(yīng)商設(shè)備封裝： 572-FBGA
Chapter 1: Device Datasheet for Arria II Devices
1–13
Electrical Characteristics
December 2013
Altera Corporation
Table 1–17 lists the pin capacitance for Arria II GZ devices.
Internal Weak Pull-Up and Weak Pull-Down Resistors
Table 1–18 lists the weak pull-up and pull-down resistor values for Arria II GX
devices.
Table 1–17. Pin Capacitance for Arria II GZ Devices
Symbol
Description
Typical
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
4
pF
CIOLR
Input capacitance on the left and right I/O pins
4
pF
CCLKTB
Input capacitance on the top and bottom non-dedicated clock input pins
4
pF
CCLKLR
Input capacitance on the left and right non-dedicated clock input pins
4
pF
COUTFB
Input capacitance on the dual-purpose clock output and feedback pins
5
pF
CCLK1, CCLK3, CCLK8,
and CCLK10
Input capacitance for dedicated clock input pins
2
pF
Table 1–18. Internal Weak Pull-up and Weak Pull-Down Resistors for Arria II GX Devices
Symbol
Description
Conditions
Min
Typ
Max
Unit
RPU
Value of I/O pin pull-up resistor
before and during configuration,
as well as user mode if the
programmable pull-up resistor
option is enabled.
VCCIO = 3.3 V ±5% (2)
725
41
k
VCCIO = 3.0 V ±5% (2)
728
47
k
VCCIO = 2.5 V ±5% (2)
835
61
k
VCCIO = 1.8 V ±5% (2)
10
57
108
k
VCCIO = 1.5 V ±5% (2)
13
82
163
k
VCCIO = 1.2 V ±5% (2)
19
143
351
k
RPD
Value of TCK pin pull-down
resistor
VCCIO = 3.3 V ±5%
6
19
29
k
VCCIO = 3.0 V ±5%
6
22
32
k
VCCIO = 2.5 V ±5%
6
25
42
k
VCCIO = 1.8 V ±5%
7
35
70
k
VCCIO = 1.5 V ±5%
8
50
112
k
Notes to Table 1–18:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for
JTAG TCK.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2AGX125DF25C5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125DF25C5NES 制造商:Altera Corporation 功能描述:IC ARRIA II GX FPGA 572FBGA 制造商:Altera Corporation 功能描述:IC FPGA 260 I/O 572FBGA
EP2AGX125DF25C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125DF25C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125DF25C6NES 制造商:Altera Corporation 功能描述:FPGA Arria
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