參數(shù)資料
型號: EP2AGX260FF35I5
廠商: Altera
文件頁數(shù): 8/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX 260K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Arria II GX
LAB/CLB數(shù): 10260
邏輯元件/單元數(shù): 244188
RAM 位總計(jì): 12038144
輸入/輸出數(shù): 612
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
1–8
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
December 2013
Altera Corporation
I/O Pin Leakage Current
Table 1–7 lists the Arria II GX I/O pin leakage current specifications.
Table 1–8 lists the Arria II GZ I/O pin leakage current specifications.
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–9 lists bus hold specifications for Arria II GX devices.
Table 1–7. I/O Pin Leakage Current for Arria II GX Devices
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–10
10
A
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–10
10
A
Table 1–8. I/O Pin Leakage Current for Arria II GZ Devices
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–20
20
A
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–20
20
A
Table 1–9. Bus Hold Parameters for Arria II GX Devices (Note 1)
Parameter
Symbol
Cond.
VCCIO (V)
Unit
1.2
1.5
1.8
2.5
3.0
3.3
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold
low,
sustaining
current
ISUSL
VIN > VIL
(max.)
8
12
30—50
70
70
A
Bus-hold
high,
sustaining
current
ISUSH
VIN < VIL
(min.)
–8
–12
–30
–50
–70
–70
A
Bus-hold
low,
overdrive
current
IODL
0V <VIN <
VCCIO
125
175
200
300
500
500
A
Bus-hold
high,
overdrive
current
IODH
0V <VIN <
VCCIO
–125
–175
–200
–300
–500
–500
A
Bus-hold
trip point
VTRIP
0.3
0.9
0.375
1.125
0.68
1.07
0.7
1.7
0.8
2
0.8
2
V
Note to Table 1–9:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
相關(guān)PDF資料
PDF描述
93LC46BT-E/SN IC EEPROM 1KBIT 2MHZ 8SOIC
HMC43DRYH-S734 CONN EDGECARD 86POS DIP .100 SLD
ASC36DRAN-S734 CONN EDGECARD 72POS .100 R/A PCB
ASC36DRAH-S734 CONN EDGECARD 72POS .100 R/A PCB
93LC56AT-I/MS IC EEPROM 2KBIT 3MHZ 8MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2AGX260FF35I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45CU17C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45CU17C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45CU17C5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45CU17C5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256