參數(shù)資料
型號: EP2AGX260FF35I5N
廠商: Altera
文件頁數(shù): 58/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX 260K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Arria II GX
LAB/CLB數(shù): 10260
邏輯元件/單元數(shù): 244188
RAM 位總計: 12038144
輸入/輸出數(shù): 612
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
Chapter 1: Device Datasheet for Arria II Devices
1–53
Switching Characteristics
December 2013
Altera Corporation
Core Performance Specifications for the Arria II Device Family
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), embedded memory, configuration, and JTAG specifications for
Arria II GX and GZ devices.
Clock Tree Specifications
Table 1–42 lists the clock tree specifications for Arria II GX devices.
Table 1–43 lists the clock tree specifications for Arria II GZ devices.
PLL Specifications
Table 1–44 lists the PLL specifications for Arria II GX devices.
Table 1–42. Clock Tree Performance for Arria II GX Devices
Clock Network
Performance
Unit
I3, C4
C5,I5
C6
GCLK and RCLK
500
400
MHz
PCLK
420
350
280
MHz
Table 1–43. Clock Tree Performance for Arria II GZ Devices
Clock Network
Performance
Unit
–C3 and –I3
–C4 and –I4
GCLK and RCLK
700
500
MHz
PCLK
500
450
MHz
Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3)
Symbol
Description
Min
Typ
Max
Unit
fIN
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–4 Speed Grade)
5
670 (1)
MHz
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–5 Speed Grade)
5
622 (1)
MHz
Input clock frequency (from clock input pins residing in
right/top/bottom banks) (–6 Speed Grade)
5
500 (1)
MHz
fINPFD
Input frequency to the PFD
5
325
MHz
fVCO
PLL VCO operating Range (2)
600
1,400
MHz
fINDUTY
Input clock duty cycle
40
60
%
fEINDUTY
External feedback clock input duty cycle
40
60
%
tINCCJ (3),
Input clock cycle-to-cycle jitter (Frequency
100 MHz)
0.15
UI (p–p)
Input clock cycle-to-cycle jitter (Frequency
100 MHz)
±750
ps (p–p)
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