參數(shù)資料
型號(hào): EP2AGX45DF29C5N
廠商: Altera
文件頁(yè)數(shù): 65/90頁(yè)
文件大小: 0K
描述: IC ARRIA II GX FPGA 45K 780FBGA
產(chǎn)品培訓(xùn)模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 4
系列: Arria II GX
LAB/CLB數(shù): 1805
邏輯元件/單元數(shù): 42959
RAM 位總計(jì): 3517440
輸入/輸出數(shù): 364
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 780-BBGA
供應(yīng)商設(shè)備封裝: 780-FBGA(29x29)
其它名稱: 544-2642
1–60
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Configuration
Table 1–50 lists the configuration mode specifications for Arria II GX and GZ devices.
JTAG Specifications
Table 1–51 lists the JTAG timing parameters and values for Arria II GX and GZ
devices.
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–52 lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX
and GZ devices.
Table 1–50. Configuration Mode Specifications for Arria II Devices
Programming Mode
DCLK Frequency
Unit
Min
Typ
Max
Passive serial
125
MHz
Fast passive parallel
125
MHz
Fast active serial (fast clock)
17
26
40
MHz
Fast active serial (slow clock)
8.5
13
20
MHz
Remote update only in fast AS mode
10
MHz
Table 1–51. JTAG Timing Parameters and Values for Arria II Devices
Symbol
Description
Min
Max
Unit
tJCP
TCK clock period
30
ns
tJCH
TCK clock high time
14
ns
tJCL
TCK clock low time
14
ns
tJPSU (TDI)
TDI JTAG port setup time
1
ns
tJPSU (TMS)
TMS JTAG port setup time
3
ns
tJPH
JTAG port hold time
5
ns
tJPCO
JTAG port clock to output
11
ns
tJPZX
JTAG port high impedance to valid output
14
ns
tJPXZ
JTAG port valid output to high impedance
14
ns
Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices
Description
Min
Typ
Max
Unit
Dev_CLRn
500
s
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