參數(shù)資料
型號: EP2AGX65DF25C6
廠商: Altera
文件頁數(shù): 59/90頁
文件大小: 0K
描述: IC ARRIA II GX FPGA 65K 572FBGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 5
系列: Arria II GX
LAB/CLB數(shù): 2530
邏輯元件/單元數(shù): 60214
RAM 位總計: 5371904
輸入/輸出數(shù): 252
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 572-FBGA
供應商設備封裝: 572-FBGA
1–54
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
fOUT
Output frequency for internal global or regional clock
(–4 Speed Grade)
500
MHz
Output frequency for internal global or regional clock
(–5 Speed Grade)
500
MHz
Output frequency for internal global or regional clock
(–6 Speed Grade)
400
MHz
fOUT_EXT
Output frequency for external clock output (–4 Speed Grade)
670 (5)
MHz
Output frequency for external clock output (–5 Speed Grade)
622 (5)
MHz
Output frequency for external clock output (–6 Speed Grade)
500 (5)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tOUTPJ_DC
Dedicated clock output period jitter (fOUT 100 MHz)
300
ps (p–p)
Dedicated clock output period jitter (fOUT 100 MHz)
30
mUI (p–p)
tOUTCCJ_DC
Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz)
300
ps (p–p)
Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz)
30
mUI (p–p)
fOUTPJ_IO
Regular I/O clock output period jitter (fOUT 100 MHz)
650
ps (p–p)
Regular I/O clock output period jitter (fOUT 100 MHz)
65
mUI (p–p)
fOUTCCJ_IO
Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz)
650
ps (p–p)
Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz)
65
mUI (p–p)
tCONFIGPLL
Time required to reconfigure PLL scan chains
3.5
SCANCLK
cycles
tCONFIGPHASE Time required to reconfigure phase shift
1
SCANCLK
cycles
fSCANCLK
SCANCLK frequency
100
MHz
tLOCK
Time required to lock from end of device configuration
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
——
1
ms
fCL B W
PLL closed-loop low bandwidth
0.3
MHz
PLL closed-loop medium bandwidth
1.5
MHz
PLL closed-loop high bandwidth
4
MHz
tPLL_PSERR
Accuracy of PLL phase shift
±50
ps
tARESET
Minimum pulse width on areset signal
10
ns
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
Symbol
Description
Min
Typ
Max
Unit
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相關代理商/技術參數(shù)
參數(shù)描述
EP2AGX65DF25C6ES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX65DF25C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF25C6NES 制造商:Altera Corporation 功能描述:FPGA Arria 制造商:Altera Corporation 功能描述:FPGA Arria? II GX Family 60214 Cells 400MHz 40nm Technology 0.9V 572-Pin FC-FBGA 制造商:Altera Corporation 功能描述:IC ARRIA II GX FPGA 572FBGA
EP2AGX65DF25I3 功能描述:IC ARRIA II GX FPGA 65K 572FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Arria II GX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA(34.55x34.55)
EP2AGX65DF25I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256