參數資料
型號： EP2AGX65DF25I5N
廠商： Altera
文件頁數： 15/90頁
文件大?。?/td> 0K
描述： IC ARRIA II GX FPGA 65K 572FBGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 5
系列： Arria II GX
LAB/CLB數： 2530
邏輯元件/單元數： 60214
RAM 位總計： 5371904
輸入/輸出數： 252
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 572-FBGA
供應商設備封裝： 572-FBGA
1–14
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
December 2013
Altera Corporation
Table 1–19 lists the weak pull-up resistor values for Arria II GZ devices.
Hot Socketing
Table 1–20 lists the hot-socketing specification for Arria II GX and GZ devices.
Schmitt Trigger Input
The Arria II GX device supports Schmitt trigger input on the TDI, TMS, TCK, nSTATUS,
nCONFIG
, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces
hysteresis to the input signal for improved noise immunity, especially for signals with
slow edge rates.
Table 1–21 lists the hysteresis specifications across the supported VCCIO range for
Schmitt trigger inputs in Arria II GX devices.
Table 1–19. Internal Weak Pull-Up Resistor for Arria II GZ Devices
Symbol
Description
Conditions
Min
Typ
Max
Unit
RPU
Value of the I/O pin pull-up
resistor before and during
configuration, as well as user
mode if the programmable
pull-up resistor option is enabled.
VCCIO = 3.0 V ±5% (3)
—25
—
k
VCCIO = 2.5 V ±5% (3)
—25
—
k
VCCIO = 1.8 V ±5% (3)
—25
—
k
VCCIO = 1.5 V ±5% (3)
—25
—
k
VCCIO = 1.2 V ±5% (3)
—25
—
k
Notes to Table 1–19:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
Table 1–20. Hot Socketing Specifications for Arria II Devices
Symbol
Description
Maximum
IIIOPIN(DC)
DC current per I/O pin
300
A
IIOPIN(AC)
AC current per I/O pin
8 mA (1)
IXCVRTX(DC)
DC current per transceiver TX pin
100 mA
IXCVRRX(DC)
DC current per transceiver RX pin
50 mA
Note to Table 1–20:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which “C” is I/O pin
capacitance and “dv/dt” is slew rate.
Table 1–21. Schmitt Trigger Input Hysteresis Specifications for Arria II GX Devices
Symbol
Description
Condition (V)
Minimum
Unit
VSchmitt
Hysteresis for Schmitt trigger input
VCCIO = 3.3
220
mV
VCCIO = 2.5
180
mV
VCCIO = 1.8
110
mV
VCCIO = 1.5
70
mV
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EP2AGX65DF29C4 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C5 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C5N 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C6 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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