參數(shù)資料
型號(hào): EP2AGX65DF29C5
廠商: Altera
文件頁(yè)數(shù): 77/90頁(yè)
文件大小: 0K
描述: IC ARRIA II GX FPGA 65K 780FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 4
系列: Arria II GX
LAB/CLB數(shù): 2530
邏輯元件/單元數(shù): 60214
RAM 位總計(jì): 5371904
輸入/輸出數(shù): 364
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 780-BBGA
供應(yīng)商設(shè)備封裝: 780-FBGA(29x29)
Chapter 1: Device Datasheet for Arria II Devices
1–71
Switching Characteristics
December 2013
Altera Corporation
Table 1–63 lists the memory output clock jitter specifications for Arria II GZ devices.
Duty Cycle Distortion (DCD) Specifications
Table 1–64 lists the worst-case DCD specifications for Arria II GX devices.
Table 1–65 lists the worst-case DCD specifications for Arria II GZ devices.
Table 1–63. Memory Output Clock Jitter Specification for Arria II GZ Devices (Note 1), (2), (3)
Parameter
Clock
Network
Symbol
–3
–4
Unit
Min
Max
Min
Max
Clock period jitter
Regional
t
JIT(per)
-55
55
-55
55
ps
Cycle-to-cycle period jitter
Regional
t
JIT(cc)
-110
110
-110
110
ps
Duty cycle jitter
Regional
t
JIT(duty)
-82.5
82.5
-82.5
82.5
ps
Clock period jitter
Global
t
JIT(per)
-82.5
82.5
-82.5
82.5
ps
Cycle-to-cycle period jitter
Global
t
JIT(cc)
-165
165
-165
165
ps
Duty cycle jitter
Global
t
JIT(duty)
-90
90
-90
90
ps
Notes to Table 1–63:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–63 is applicable when an input jitter of 30 ps is applied.
Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GX Devices (Note 1)
Symbol
C4
I3, C5, I5
C6
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Note to Table 1–64:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices (Note 1)
Symbol
C3, I3
C4, I4
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Note to Table 1–65:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
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EP2AGX65DF29C5N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF29C6NES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX65DF29I3 功能描述:IC ARRIA II GX FPGA 65K 780FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Arria II GX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)