參數資料
型號: EP2AGX95EF29C6
廠商: Altera
文件頁數: 76/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX FPGA 95K 780FBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 4
系列: Arria II GX
LAB/CLB數: 3747
邏輯元件/單元數: 89178
RAM 位總計: 6839296
輸入/輸出數: 372
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 780-BBGA
供應商設備封裝: 780-FBGA(29x29)
1–70
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Table 1–60 lists the DQS phase shift error for Arria II GX devices.
Table 1–61 lists the DQS phase shift error for Arria II GZ devices.
Table 1–62 lists the memory output clock jitter specifications for Arria II GX devices.
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria II GX
Devices (Note 1)
Number of DQS Delay Buffer
C4
I3, C5, I5
C6
Unit
1
263036
ps
2
526072
ps
3
78
90
108
ps
4
104
120
144
ps
Note to Table 1–60:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a C4 speed grade is ± 78 ps or ± 39 ps.
Table 1–61. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria II GZ
Devices (Note 1)
Number of DQS Delay Buffer
–3
–4
Unit
128
30
ps
256
60
ps
384
90
ps
4
112
120
ps
Note to Table 1–61:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a 3 speed grade is ± 84 ps or ± 42 ps.
Table 1–62. Memory Output Clock Jitter Specification for Arria II GX Devices (Note 1), (2), (3)
Parameter
Clock
Network
Symbol
–4
–5
–6
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
Global
t
JIT(per)
-100
100
-125
125
-125
125
ps
Cycle-to-cycle period
jitter
Global
t
JIT(cc)
-200
200
-250
250
-250
250
ps
Duty cycle jitter
Global
t
JIT(duty)
-100
100
-125
125
-125
125
ps
Notes to Table 1–62:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
(3) The memory output clock jitter stated in Table 1–62 is applicable when an input jitter of 30 ps is applied.
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參數描述
EP2AGX95EF29C6N 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 3747 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX95EF29I3 功能描述:IC ARRIA II GX FPGA 95K 780FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:Arria II GX 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數:100 邏輯元件/單元數:238 RAM 位總計:3200 輸入/輸出數:80 門數:3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA(34.55x34.55)
EP2AGX95EF29I3N 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 3747 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX95EF29I5 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 3747 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX95EF29I5N 功能描述:FPGA - 現場可編程門陣列 FPGA - Arria II GX 3747 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256