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參數(shù)資料
| 型號(hào)： | EP2S60F1020C3 |
| 廠商： | Altera |
| 文件頁數(shù)： | 461/768頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II FPGA 60K 1020-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 6 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 3022 |
| 邏輯元件/單元數(shù)： | 60440 |
| RAM 位總計(jì)： | 2544192 |
| 輸入/輸出數(shù)： | 718 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1020-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1020-FBGA（33x33） |
| 配用： | 544-1700-ND - DSP KIT W/STRATIX II EP2S60N 544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N |
| 其它名稱： | 544-1130 EP2S60F1020C3ES |
Altera Corporation
5–29
January 2008
Stratix II Device Handbook, Volume 2
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Referenced
Documents
This chapter references the following documents:
■
DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook
■
DC & Switching Characteristics chapter in volume 1 of the
Stratix II GX Device Handbook
■
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II Handbook
■
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Handbook
■
volume 2 of the Stratix II Device Handbook
■
Stratix II Device Family Data Sheet in volume 1 of the Stratix II Device
Handbook
Document
Revision History
Table 5–5 shows the revision history for this chapter.
Table 5–5. Document Revision History (Part 1 of 2)
Date and
Document Version
Changes Made
Summary of Changes
January 2008, v2.2 Updated Figure 5–2.—
Added “Referenced Documents” section.
—
Minor text edits.
—
Added Figure 5–9.—
Updated “Receiver Data Realignment Circuit”.—
For the Stratix II GX Device Handbook only:
Formerly chapter 10. The chapter number changed
due to the addition of the Stratix II GX Dynamic
Reconfiguration chapter.
—
May 2007, v2.1
Updated entire chapter to include Stratix II GX
information.
—
Changed chapter part number.
—
Fixed two types in “High-Speed Differential I/Os
and Single-Ended I/Os” section
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S60F1020C3N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 3022 LABs 718 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F1020C3NGA | 制造商:Altera 功能描述:EP2S60F1020C3NGA |
| EP2S60F1020C4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 3022 LABs 718 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F1020C4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 3022 LABs 718 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S60F1020C5 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 3022 LABs 718 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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