參數(shù)資料
型號: EP4CE10E22I7
廠商: Altera
文件頁數(shù): 24/42頁
文件大小: 0K
描述: IC CYCLONE IV FPGA 10K 144EQFP
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標準包裝: 120
系列: CYCLONE® IV E
LAB/CLB數(shù): 645
邏輯元件/單元數(shù): 10320
RAM 位總計: 423936
輸入/輸出數(shù): 91
電源電壓: 1.15 V ~ 1.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 144-EQFP(20x20)
1–30
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
tLOCK (2)
1
1
—1
1—
1
ms
Notes to Table 1–32:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX
devices.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK (input
clock
frequency)
×10
5
200
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×8
5
200
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×7
5
200
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×4
5
200
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×2
5
200
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×1
5
400
5
311
5
311
5
311
5
265
MHz
Device
operation in
Mbps
×10
100
400
100
311
100
311
100
311
100
265
Mbps
×8
80
400
80
311
80
311
80
311
80
265
Mbps
×7
70
400
70
311
70
311
70
311
70
265
Mbps
×4
40
400
40
311
40
311
40
311
40
265
Mbps
×2
20
400
20
311
20
311
20
311
20
265
Mbps
×1
10
400
10
311
10
311
10
311
10
265
Mbps
tDUTY
45
55
45
55
45
55
45
55
45
55
%
TCCS
200
200
200
200
200
ps
Output jitter
(peak to peak)
500
500
550
600
700
ps
tRISE
20 – 80%,
CLOAD =
5pF
500
500
500
500
500
ps
tFALL
20 – 80%,
CLOAD =
5pF
500
500
500
500
500
ps
tLOCK (3)
—1—
1
1
1
1
ms
Notes to Table 1–33:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at
the output pin of all I/O banks.
Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the
output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(3) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
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