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    參數(shù)資料
    

    


    


    
型號(hào)：
EP4CE115F29C8

    

    
廠商：
Altera

    

    
文件頁(yè)數(shù)：
13/42頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC CYCLONE IV FPGA 115K 780-FBGA

    

    
產(chǎn)品培訓(xùn)模塊：
Three Reasons to Use FPGA's in Industrial Designs
    
	Cyclone IV FPGA Family Overview
    		

    

    
特色產(chǎn)品：
Cyclone? IV FPGAs
    		

    

    
標(biāo)準(zhǔn)包裝：
36

    

    
系列：
CYCLONE® IV E

    

    
LAB/CLB數(shù)：
7155
    		

    

    
邏輯元件/單元數(shù)：
114480
    		

    

    
RAM 位總計(jì)：
3981312
    		

    

    
輸入/輸出數(shù)：
528
    		

    

    
電源電壓：
1.15 V ~ 1.25 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
780-BBGA
    		

    

    
供應(yīng)商設(shè)備封裝：
780-FBGA（29x29）
    		

    

    

    

	
    
    
    

    
    
	
    1–20
    Chapter 1: Cyclone IV Device Datasheet
    Switching Characteristics
    December 2013
    Altera Corporation
    PLD-Transceiver Interface
    Interface speed
    (F324 and smaller
    package)
    —
    25
    —
    125
    25
    —
    125
    25
    —
    125
    MHz
    Interface speed
    (F484 and larger
    package)
    —
    25
    —
    156.25
    25
    —
    156.25
    25
    —
    156.25
    MHz
    Digital reset pulse
    width
    —
    Minimum is 2 parallel clock cycles
    Notes to Table 1–21:
    (1) This specification is valid for transmitter output jitter specification with a maximum total jitter value of 112 ps, typically for 3.125 Gbps SRIO and XAUI
    protocols.
    (2) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk frequency
    is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode.
    (3) The device cannot tolerate prolonged operation at this absolute maximum.
    (4) The rate matcher supports only up to ±300 parts per million (ppm).
    (5) Supported for the N148, F169, and F324 device packages only.
    (6) Supported for the F484, F672, and F896 device packages only. Pending device characterization.
    (7) To support CDR ppm tolerance greater than ±300 ppm, implement ppm detector in user logic and configure CDR to Manual Lock Mode.
    (8) Asynchronous spread-spectrum clocking is not supported.
    (9) For the EP4CGX30 (F484 package only), EP4CGX50, and EP4CGX75 devices, the CDR ppl tolerance is ±200 ppm.
    (10) Time taken until pll_locked goes high after pll_powerdown deasserts.
    (11) Time that the CDR must be kept in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode.
    (12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode (Figure 1–2), or after rx_freqlocked signal goes high in
    automatic mode (Figure 1–3).
    (13) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode.
    (14) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode.
    (15) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
    Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)
    Symbol/
    Description
    Conditions
    C6
    C7, I7
    C8
    Unit
    Min
    Typ
    Max
    Min
    Typ
    Max
    Min
    Typ
    Max
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
EP4CE115F29C8L
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV E 7155 LABs 528 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP4CE115F29C8LN
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV E 7155 LABs 528 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP4CE115F29C8N
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV E 7155 LABs 528 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP4CE115F29C9L
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV E 7155 LABs 528 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP4CE115F29C9LN
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV E 7155 LABs 528 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
    
    
    
	
    	
    
    
     
     
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