參數(shù)資料
型號: EP4CE15F23C7
廠商: Altera
文件頁數(shù): 31/42頁
文件大小: 0K
描述: IC CYCLONE IV FPGA 15K 484FBGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標準包裝: 60
系列: CYCLONE® IV E
LAB/CLB數(shù): 963
邏輯元件/單元數(shù): 15408
RAM 位總計: 516096
輸入/輸出數(shù): 343
電源電壓: 1.15 V ~ 1.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FBGA(23x23)
Chapter 1: Cyclone IV Device Datasheet
1–37
I/O Timing
December 2013
Altera Corporation
I/O Timing
Use the following methods to determine I/O timing:
the Excel-based I/O Timing
the Quartus II timing analyzer
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone IV Devices
Literature website.
Glossary
Table 1–46 lists the glossary for this chapter.
Table 1–46. Glossary (Part 1 of 5)
Letter
Term
Definitions
A
——
B
——
C
——
D
——
E
——
F
fHSCLK
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
G
GCLK
Input pin directly to Global Clock network.
GCLK PLL
Input pin to Global Clock network through the PLL.
H
HSIODR
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
I
Input Waveforms
for the SSTL
Differential I/O
Standard
V
IL
V
REF
V
IH
VSWING
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相關代理商/技術參數(shù)
參數(shù)描述
EP4CE15F23C7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23C8L 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23C8LN 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23C8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256