參數(shù)資料
型號: EP4CE15F23I7N
廠商: Altera
文件頁數(shù): 42/42頁
文件大小: 0K
描述: IC CYCLONE IV FPGA 15K 484FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標準包裝: 60
系列: CYCLONE® IV E
LAB/CLB數(shù): 963
邏輯元件/單元數(shù): 15408
RAM 位總計: 516096
輸入/輸出數(shù): 343
電源電壓: 1.15 V ~ 1.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FBGA(23x23)
Chapter 1: Cyclone IV Device Datasheet
1–9
Operating Conditions
December 2013
Altera Corporation
The OCT resistance may vary with the variation of temperature and voltage after
calibration at device power-up. Use Table 1–10 and Equation 1–1 to determine the
final OCT resistance considering the variations after calibration at device power-up.
Table 1–10 lists the change percentage of the OCT resistance with voltage and
temperature.
Table 1–10. OCT Variation After Calibration at Device Power
-Up for Cyclone IV Devices
Nominal Voltage
dR/dT (%/°C)
dR/dV (%/mV)
3.0
0.262
–0.026
2.5
0.234
–0.039
1.8
0.219
–0.086
1.5
0.199
–0.136
1.2
0.161
–0.288
Equation 1–1. Final OCT Resistance (1), (2), (3), (4), (5), (6)
R
V = (V2 – V1) × 1000 × dR/dV –––––
R
T = (T2 – T1) × dR/dT –––––
For
R
x < 0; MFx = 1/ (|Rx|/100 + 1) –––––
For Rx > 0; MFx = Rx/100 + 1 ––––– (10)
MF = MFV × MFT ––––– (11)
Rfinal = Rinitial × MF ––––– (12)
(1) T2 is the final temperature.
(2) T1 is the initial temperature.
(3) MF is multiplication factor.
(4) Rfinal is final resistance.
(5) Rinitial is initial resistance.
(6) Subscript x refers to both V and T.
(7)
R
V is a variation of resistance with voltage.
(8)
R
T is a variation of resistance with temperature.
(9) dR/dT is the change percentage of resistance with temperature after calibration at device power
-up.
(10) dR/dV is the change percentage of resistance with voltage after calibration at device power
-up.
(11) V2 is final voltage.
(12) V1 is the initial voltage.
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