參數資料
型號: EP4CE22F17I8L
廠商: Altera
文件頁數: 7/42頁
文件大?。?/td> 0K
描述: IC CYCLONE IV FPGA 22K 256FBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產品: Cyclone? IV FPGAs
標準包裝: 90
系列: CYCLONE® IV E
LAB/CLB數: 1395
邏輯元件/單元數: 22320
RAM 位總計: 608256
輸入/輸出數: 153
電源電壓: 0.97 V ~ 1.03 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BGA
供應商設備封裝: 256-FBGA(17x17)
Chapter 1: Cyclone IV Device Datasheet
1–15
Operating Conditions
December 2013
Altera Corporation
LVDS
(Column
I/Os)
2.375
2.5
2.625
100
0.05
DMAX 500 Mbps
1.80
247
600
1.125
1.25
1.375
0.55
500 Mbps
D
MAX
700 Mbps
1.80
1.05
DMAX > 700 Mbps
1.55
BLVDS (Row
I/Os) (4)
2.375
2.5
2.625
100
BLVDS
(Column
I/Os) (4)
2.375
2.5
2.625
100
mini
-LVDS
(Row I/Os)
2.375
2.5
2.625
300
600
1.0
1.2
1.4
mini
-LVDS
(Column
I/Os) (5)
2.375
2.5
2.625
300
600
1.0
1.2
1.4
RSDS (Row
I/Os) (5)
2.375
2.5
2.625
100
200
600
0.5
1.2
1.5
RSDS
(Column
I/Os) (5)
2.375
2.5
2.625
100
200
600
0.5
1.2
1.5
PPDS (Row
I/Os) (5)
2.375
2.5
2.625
100
200
600
0.5
1.2
1.4
PPDS
(Column
I/Os) (5)
2.375
2.5
2.625
100
200
600
0.5
1.2
1.4
Notes to Table 1–20:
(1) For an explanation of terms used in Table 1–20, refer to “Glossary” on page 1–37.
(2) VIN range: 0 V VIN 1.85 V.
(3) RL range: 90 RL 110 .
(4) There are no fixed VIN, VOD, and VOS specifications for BLVDS. They depend on the system topology.
(5) The Mini
-LVDS, RSDS, and PPDS standards are only supported at the output pins.
(6) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins.
Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices (1) (Part 2 of 2)
I/O Standard
VCCIO (V)
VID (mV)
VIcM (V) (2)
VOD (mV) (3)
VOS (V) (3)
Min
Typ
Max
Min
Max
Min
Condition
Max
Min
Typ
Max
Min
Typ
Max
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