參數(shù)資料
型號: EP4CGX150DF31I7N
廠商: Altera
文件頁數(shù): 11/42頁
文件大?。?/td> 0K
描述: IC CYCLONE IV FPGA 150K 896FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 27
系列: CYCLONE® IV GX
LAB/CLB數(shù): 9360
邏輯元件/單元數(shù): 149760
RAM 位總計: 6635520
輸入/輸出數(shù): 475
電源電壓: 1.16 V ~ 1.24 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 896-BBGA
供應(yīng)商設(shè)備封裝: 896-FBGA(31x31)
Chapter 1: Cyclone IV Device Datasheet
1–19
Switching Characteristics
December 2013
Altera Corporation
Signal detect/loss
threshold
PIPE mode
65
175
65
175
65
175
mV
tLTR (10)
75
75——
75
s
tLTR-LTD_Manual (11)
15—
15
—15—
s
tLTD (12)
0
100
4000
0
100
4000
0
100
4000
ns
tLTD_Manual (13)
4000
4000
4000
ns
tLTD_Auto (14)
4000
4000
4000
ns
Receiver buffer and
CDR offset
cancellation time
(per channel)
17000
17000
17000
recon
fig_c
lk
cycles
Programmable DC
gain
DC Gain Setting =
0
—0
0
0
dB
DC Gain Setting =
1
—3
3
3
dB
DC Gain Setting =
2
—6
6
6
dB
Transmitter
Supported I/O
Standards
1.5 V PCML
Data rate (F324 and
smaller package)
600
2500
600
2500
600
2500
Mbps
Data rate (F484 and
larger package)
600
3125
600
3125
600
2500
Mbps
VOCM
0.65 V setting
650
650
650
mV
Differential on-chip
termination resistors
100
setting
100
100
100
150
setting
150
150
150
Differential and
common mode
return loss
PIPE, CPRI LV,
Serial Rapid I/O
SR, SDI, XAUI,
SATA
Compliant
Rise time
50
200
50
200
50
200
ps
Fall time
50
200
50
200
50
200
ps
Intra-differential pair
skew
15
15
15
ps
Intra-transceiver
block skew
120
120
120
ps
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 3 of 4)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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