參數(shù)資料
型號(hào)： EP4CGX30CF23I7N
廠商： Altera
文件頁(yè)數(shù)： 28/42頁(yè)
文件大小： 0K
描述： IC CYCLONE IV GX FPGA 30K 484FBG
產(chǎn)品培訓(xùn)模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 60
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 1840
邏輯元件/單元數(shù)： 29440
RAM 位總計(jì)： 1105920
輸入/輸出數(shù)： 290
電源電壓： 1.16 V ~ 1.24 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FBGA（23x23）
1–34
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
IOE Programmable Delay
Table 1–40 and Table 1–41 list the IOE programmable delay for Cyclone IV E 1.0 V
core voltage devices.
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)
Parameter
Paths Affected
Number
of
Setting
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
C8L
I8L
C8L
C9L
I8L
Input delay from pin to
internal cells
Pad to I/O
dataout to core
7
0
2.054
1.924
3.387
4.017
3.411
ns
Input delay from pin to
input register
Pad to I/O input
register
8
0
2.010
1.875
3.341
4.252
3.367
ns
Delay from output register
to output pin
I/O output
register to pad
2
0
0.641
0.631
1.111
1.377
1.124
ns
Input delay from
dual-purpose clock pin to
fan-out destinations
Pad to global
clock network
12
0
0.971
0.931
1.684
2.298
1.684
ns
Notes to Table 1–40:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–41. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)
Parameter
Paths Affected
Number
of
Setting
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
C8L
I8L
C8L
C9L
I8L
Input delay from pin to
internal cells
Pad to I/O
dataout to core
7
0
2.057
1.921
3.389
4.146
3.412
ns
Input delay from pin to
input register
Pad to I/O input
register
8
0
2.059
1.919
3.420
4.374
3.441
ns
Delay from output register
to output pin
I/O output
register to pad
2
0
0.670
0.623
1.160
1.420
1.168
ns
Input delay from
dual-purpose clock pin to
fan-out destinations
Pad to global
clock network
12
0
0.960
0.919
1.656
2.258
1.656
ns
Notes to Table 1–41:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
相關(guān)PDF資料
PDF描述
EP4CGX30CF23C6N IC CYCLONE IV GX FPGA 30K 484FBG
FSM24DSEN-S243 CONN EDGECARD 48POS .156 EYELET
A42MX16-1PQG208I IC FPGA MX SGL CHIP 24K 208-PQFP
A42MX16-2PQG208 IC FPGA MX SGL CHIP 24K 208-PQFP
FSM24DSEH-S243 CONN EDGECARD 48POS .156 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4CGX30F17C8 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX30F23C8N 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview
EP4CGX30F23I7N 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Cyclone IV Device Datasheet
EP4CGX50 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview
EP4CGX50CF23C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone IV GX 3118 LABs 290 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*