參數(shù)資料
型號： EP4CGX50DF27C7N
廠商： Altera
文件頁數(shù)： 3/42頁
文件大小： 0K
描述： IC CYCLONE IV FPGA 50K 672-FBGA
產(chǎn)品培訓模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標準包裝： 40
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 3118
邏輯元件/單元數(shù)： 49888
RAM 位總計： 2562048
輸入/輸出數(shù)： 310
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BGA
供應商設備封裝： 672-FBGA（27x27）
其它名稱： 544-2732
Chapter 1: Cyclone IV Device Datasheet
1–11
Operating Conditions
December 2013
Altera Corporation
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 1–12 lists the weak pull-up and pull-down resistor values for Cyclone IV
devices.
Hot-Socketing
Table 1–13 lists the hot-socketing specifications for Cyclone IV devices.
1 During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin
capacitance is less than 20 pF.
Table 1–12. Internal Weak Pull
-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R_PU
Value of the I/O pin pull-up resistor
before and during configuration, as
well as user mode if you enable the
programmable pull-up resistor option
VCCIO = 3.3 V ± 5% (2), (3)
725
41
k
VCCIO = 3.0 V ± 5% (2), (3)
728
47
k
VCCIO = 2.5 V ± 5% (2), (3)
835
61
k
VCCIO = 1.8 V ± 5% (2), (3)
10
57
108
k
VCCIO = 1.5 V ± 5% (2), (3)
13
82
163
k
VCCIO = 1.2 V ± 5% (2), (3)
19
143
351
k
R_PD
Value of the I/O pin pull-down resistor
before and during configuration
VCCIO = 3.3 V ± 5% (4)
619
30
k
VCCIO = 3.0 V ± 5% (4)
622
36
k
VCCIO = 2.5 V ± 5% (4)
625
43
k
VCCIO = 1.8 V ± 5% (4)
735
71
k
VCCIO = 1.5 V ± 5% (4)
8
50
112
k
Notes to Table 1–12:
(1) All I/O pins have an option to enable weak pull
-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG TCK.
(2) Pin pull
-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) R_PU = (VCCIO –VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC –5%;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Table 1–13. Hot
-Socketing Specifications for Cyclone IV Devices
Symbol
Parameter
Maximum
IIOPIN(DC)
DC current per I/O pin
300
A
IIOPIN(AC)
AC current per I/O pin
8 mA (1)
IXCVRTX(DC)
DC current per transceiver TX pin
100 mA
IXCVRRX(DC)
DC current per transceiver RX pin
50 mA
Note to Table 1–13:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
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相關代理商/技術參數(shù)
參數(shù)描述
EP4CGX50DF27C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 3118 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX50DF27C8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 3118 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX50DF27I7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 3118 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX50DF27I7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 3118 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX50F17C8 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet
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