參數(shù)資料
型號: EP4CGX50DF27I7N
廠商: Altera
文件頁數(shù): 10/42頁
文件大?。?/td> 0K
描述: IC CYCLONE IV GX FPGA 50K 672FBG
產(chǎn)品培訓(xùn)模塊: Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 40
系列: CYCLONE® IV GX
LAB/CLB數(shù): 3118
邏輯元件/單元數(shù): 49888
RAM 位總計: 2562048
輸入/輸出數(shù): 310
電源電壓: 1.16 V ~ 1.24 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 672-BGA
供應(yīng)商設(shè)備封裝: 672-FBGA(27x27)
1–18
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
Receiver
Supported I/O
Standards
1.4 V PCML,
1.5 V PCML,
2.5 V PCML,
LVPECL, LVDS
Data rate (F324 and
smaller package) (15)
600
2500
600
2500
600
2500
Mbps
Data rate (F484 and
larger package) (15)
600
3125
600
3125
600
2500
Mbps
Absolute VMAX for a
receiver pin (3)
1.6
1.6
1.6
V
Operational VMAX for
a receiver pin
1.5
1.5
1.5
V
Absolute VMIN for a
receiver pin
–0.4
–0.4
–0.4
V
Peak-to-peak
differential input
voltage VID (diff p-p)
VICM = 0.82 V
setting, Data Rate
= 600 Mbps to
3.125 Gbps
0.1
2.7
0.1
2.7
0.1
2.7
V
VICM
VICM = 0.82 V
setting
820 ±
10%
——
820 ±
10%
——
820 ±
10%
—mV
Differential on-chip
termination resistors
100
setting
100
100
100
150
setting
150
150
150
Differential and
common mode
return loss
PIPE, Serial
Rapid I/O SR,
SATA, CPRI LV,
SDI, XAUI
Compliant
Programmable ppm
detector (4)
± 62.5, 100, 125, 200,
250, 300
ppm
Clock data recovery
(CDR) ppm
tolerance (without
spread-spectrum
clocking enabled)
——
±300 (5),
±350
——
±300
±350
——
±300
±350
ppm
CDR ppm tolerance
(with synchronous
spread-spectrum
clocking enabled) (8)
——
350 to
–5350
——
350 to
–5350
——
350 to
–5350
ppm
Run length
80
80
80
UI
Programmable
equalization
No Equalization
1.5
1.5
1.5
dB
Medium Low
4.5
4.5
4.5
dB
Medium High
5.5
5.5
5.5
dB
High
7
7
7
dB
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 2 of 4)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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