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參數(shù)資料
| 型號： | EP4S100G4F45I3 |
| 廠商： | Altera |
| 文件頁數(shù)： | 22/22頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 360K 1932FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 14144 |
| 邏輯元件/單元數(shù)： | 353600 |
| RAM 位總計： | 23105536 |
| 輸入/輸出數(shù)： | 781 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1932-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1932-FBGA（45x45） |
Chapter 1: Overview for the Stratix IV Device Family
1–9
Architecture Features
September 2012
Altera Corporation
PLLs
■
Three to 12 PLLs per device supporting spread-spectrum input tracking,
programmable bandwidth, clock switchover, dynamic reconfiguration, and delay
compensation
■
On-chip PLL power supply regulators to minimize noise coupling
I/O Features
■
Sixteen to 24 modular I/O banks per device with 24 to 48 I/Os per bank designed
and packaged for optimal simultaneous switching noise (SSN) performance and
migration capability
■
Support for a wide range of industry I/O standards, including single-ended
(LVTTL/CMOS/PCI/PCIX), differential (LVDS/mini-LVDS/RSDS),
voltage-referenced single-ended and differential (SSTL/HSTL Class I/II) I/O
standards
■
On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration for
single-ended I/Os and on-chip differential (RD) termination for differential I/Os
■
Programmable output drive strength, slew rate control, bus hold, and weak
pull-up capability for single-ended I/Os
■
User I/O:GND:VCC ratio of 8:1:1 to reduce loop inductance in the package—PCB
interface
■
Programmable transmitter differential output voltage (VOD) and pre-emphasis for
high-speed LVDS I/O
High-Speed Differential I/O with DPA and Soft-CDR
■
Dedicated circuitry on the left and right sides of the device to support differential
links at data rates from 150 Mbps to 1.6 Gbps
■
Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential
SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT
devices
■
DPA circuitry at the receiver automatically compensates for channel-to-channel
and channel-to-clock skew in source synchronous interfaces
■
Soft-CDR circuitry at the receiver allows implementation of asynchronous serial
interfaces with embedded clocks at up to 1.6 Gbps data rate (SGMII and GbE)
External Memory Interfaces
■
Support for existing and emerging memory interface standards such as DDR
SDRAM, DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM, QDRII+ SRAM, and
RLDRAM II
■
DDR3 up to 1,067 Mbps/533 MHz
■
Programmable DQ group widths of 4 to 36 bits (includes parity bits)
■
Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate
register capabilities provide a robust external memory interface solution
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S100G4F45I3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5F45I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5F45I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5F45I1NGA | 制造商:Altera Corporation 功能描述: |
| EP4S100G5F45I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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