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參數(shù)資料
| 型號： | EP4S40G2F40I1 |
| 廠商： | Altera |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 230K 1517FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 9120 |
| 邏輯元件/單元數(shù)： | 228000 |
| RAM 位總計： | 17544192 |
| 輸入/輸出數(shù)： | 654 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1517-BBGA |
| 供應商設備封裝： | 1517-FBGA（40x40） |
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Table 1–2 lists the Stratix IV GX device package options.
1 On-package decoupling reduces the need for on-board or PCB decoupling capacitors by satisfying the transient current
requirements at higher frequencies. The Power Delivery Network design tool for Stratix IV devices accounts for the on-package
decoupling and reflects the reduced requirements for PCB decoupling capacitors.
Device
F780
(29 mm x 29 mm) (6)
F1152
(35 mm x 35 mm)
F1152
(35 mm x 35 mm) (5), (7)
F1517
(40 mm x 40 mm)
F1760
(42.5 mm x 42.5 mm)
F1932
(45 mm x 45 mm)
EP4SGX70
DF29
—
HF35
—
EP4SGX110
DF29
—
FF35
HF35
—
EP4SGX180
DF29
—
FF35
—
HF35
KF40
—
EP4SGX230
DF29
—
FF35
—
HF35
KF40
—
EP4SGX290
—
FH29 (3)
FF35
—
HF35
KF40
KF43
NF45
EP4SGX360
—
FH29 (3)
FF35
—
HF35
KF40
KF43
NF45
EP4SGX530
—
HH35 (4)
KH40 (4)
KF43
NF45
Notes to Table 1–2:
(1) Device packages in the same column and marked under the same arrow sign have vertical migration capability.
(2) Use the Pin Migration Viewer in the Pin Planner to verify the pin migration compatibility when migrating devices. For more information, refer to I/O Management in the Quartus II Handbook, Volume 2.
(3) The 780-pin EP4SGX290 and EP4SGX360 devices are available only in 33 mm x 33 mm Hybrid flip chip package.
(4) The 1152-pin and 1517-pin EP4SGX530 devices are available only in 42.5 mm x 42.5 mm Hybrid flip chip packages.
(5) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Package Information Datasheet for Altera Devices.
(6) Devices listed in this column are available in –2x, –3, and –4 speed grades. These devices do not have on-package decoupling capacitors.
(7) Devices listed in this column are available in –2, –3, and –4 speed grades. These devices have on-package decoupling capacitors. For more information about on-package decoupling capacitor value
in each device, refer to Table 1–3.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S40G2F40I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S40G2F40I3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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