參數資料
| 型號： | EP4SE360F35C2N |
| 廠商： | Altera |
| 文件頁數： | 72/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 360K 1152FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV E |
| LAB/CLB數： | 14144 |
| 邏輯元件/單元數： | 353600 |
| RAM 位總計： | 23105536 |
| 輸入/輸出數： | 744 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1152-BBGA |
| 供應商設備封裝： | 1152-FBGA（27x27） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
1–66
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
S
SW (sampling
window)
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Single-ended
voltage
referenced I/O
standard
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
Single-Ended Voltage Referenced I/O Standard
T
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-
to-channel-skew)
The timing difference between the fastest and slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20-80%)
U
——
Table 1–54. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
相關PDF資料 |
PDF描述 |
|---|---|
| AYM36DRMD-S664 | CONN EDGECARD 72POS .156 WW |
| EP4SE820H35C4N | IC STRATIX IV FPGA 820K 1152HBGA |
| ASM36DRMD-S664 | CONN EDGECARD 72POS .156 WW |
| AGM36DRMD-S664 | CONN EDGECARD 72POS .156 WW |
| ASM36DSAN | CONN EDGECARD 72POS R/A .156 SLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EP4SE360F35C3 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV E 14144 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SE360F35C3N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV E 14144 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SE360F35C4 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV E 14144 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SE360F35C4N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV E 14144 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SE360F35I3 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV E 14144 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復。