參數(shù)資料
型號: EP4SE360F35I4N
廠商: Altera
文件頁數(shù): 17/82頁
文件大小: 0K
描述: IC STRATIX IV FPGA 360K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 14144
邏輯元件/單元數(shù): 353600
RAM 位總計: 23105536
輸入/輸出數(shù): 744
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–16
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 1–23 lists the Stratix IV GX transceiver specifications.
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 1 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML 1.5 V PCML, 2.5 V PCML, Differential LVPECL (4), LVDS, HCSL
Input frequency
from REFCLK input
pins
50
697
50
697
50
637.5
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
50
425
50
325
50
325
MHz
Absolute VMAX for a
REFCLK
pin
1.6
1.6
1.6
V
Operational VMAX for
a REFCLK pin
1.5
1.5
1.5
V
Absolute VMIN for a
REFCLK
pin
-0.4
-0.4
-0.4
V
Rise/fall time (21)
——
0.2
0.2
0.2
UI
Duty cycle
45
55
45
55
45
55
%
Peak-to-peak
differential input
voltage
200
1600
200
1600
200
1600
mV
Spread-spectrum
modulating clock
frequency
PCIe
30
33
30
33
30
33
kHz
Spread-spectrum
downspread
PCIe
0 to
-0.5%
——
0 to
-0.5%
——
0 to
-0.5%
——
On-chip termination
resistors
100
100
100
VICM (AC coupled)
1100 ± 10%
mV
VICM (DC coupled)
HCSL I/O
standard for
PCIe reference
clock
250
550
250
550
250
550
mV
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EP4SE360H29C2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 14144 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE360H29C2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 14144 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE360H29C3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 14144 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE360H29C3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 14144 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE360H29C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 14144 LABs 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256