
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–16
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 1–23 lists the Stratix IV GX transceiver specifications.
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 1 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML 1.5 V PCML, 2.5 V PCML, Differential LVPECL
(4), LVDS, HCSL
Input frequency
from REFCLK input
pins
—
50
—
697
50
—
697
50
—
637.5
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
—
50
—
425
50
—
325
50
—
325
MHz
Absolute VMAX for a
REFCLK
pin
—
1.6
—
1.6
—
1.6
V
Operational VMAX for
a REFCLK pin
—
1.5
—
1.5
—
1.5
V
Absolute VMIN for a
REFCLK
pin
—
-0.4
—
-0.4
—
-0.4
—
V
——
—
0.2
—
0.2
—
0.2
UI
Duty cycle
—
45
—
55
45
—
55
45
—
55
%
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
200
—
1600
mV
Spread-spectrum
modulating clock
frequency
PCIe
30
—
33
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
0 to
-0.5%
——
0 to
-0.5%
——
0 to
-0.5%
——
On-chip termination
resistors
—
100
—
100
—
100
—
VICM (AC coupled)
—
1100 ± 10%
mV
VICM (DC coupled)
HCSL I/O
standard for
PCIe reference
clock
250
—
550
250
—
550
250
—
550
mV