參數(shù)資料
型號(hào): EP4SE360H29I3N
廠商: Altera
文件頁數(shù): 52/82頁
文件大小: 0K
描述: IC STRATIX IV FPGA 360K 780HBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 14144
邏輯元件/單元數(shù): 353600
RAM 位總計(jì): 23105536
輸入/輸出數(shù): 488
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 780-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 780-HBGA(33x33)
1–48
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
PLL Specifications
Table 1–34 lists the Stratix IV PLL specifications when operating in the commercial
(0° to 85°C), industrial (–40° to 100°C), and military (–55°C to 125°C) junction
temperature ranges.
Table 1–34. PLL Specifications for Stratix IV Devices (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency (–2/–2x speed grade)
5
800 (1)
MHz
Input clock frequency (–3 speed grade)
5
717 (1)
MHz
Input clock frequency (–4 speed grade)
5
717 (1)
MHz
fINPFD
Input frequency to the PFD
5
325
MHz
fVCO (2)
PLL VCO operating range (–2 speed grade)
600
1600
MHz
PLL VCO operating range (–3 speed grade)
600
1300
MHz
PLL VCO operating range (–4 speed grade)
600
1300
MHz
tEINDUTY
Input clock or external feedback clock input duty cycle
40
60
%
fOUT
Output frequency for internal global or regional clock
(–2/–2x speed grade)
800 (3)
MHz
Output frequency for internal global or regional clock
(–3 speed grade)
717 (3)
MHz
Output frequency for internal global or regional clock
(–4 speed grade)
717 (3)
MHz
fOUT_EXT
Output frequency for external clock output (–2 speed grade)
800 (3)
MHz
Output frequency for external clock output (–3 speed grade)
717 (3)
MHz
Output frequency for external clock output (–4 speed grade)
717 (3)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
10
ns
tCONFIGPLL
Time required to reconfigure scan chain
3.5
scanclk
cycles
tCONFIGPHASE
Time required to reconfigure phase shift
1
scanclk
cycles
fSCANCLK
scanclk frequency
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
de-assertion of areset
——
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
——
1
ms
fCLBW
PLL closed-loop low bandwidth
0.3
MHz
PLL closed-loop medium bandwidth
1.5
MHz
PLL closed-loop high bandwidth (8)
—4
MHz
tPLL_PSERR
Accuracy of PLL phase shift
±50
ps
tARESET
Minimum pulse width on the areset signal
10
ns
tINCCJ (4), (5)
Input clock cycle to cycle jitter (FREF ≥ 100 MHz)
0.15
UI (p-p)
Input clock cycle to cycle jitter (FREF < 100 MHz)
±750
ps (p-p)
tOUTPJ_DC (6)
Period Jitter for dedicated clock output (FOUT ≥ 100 MHz)
175
ps (p-p)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
17.5
mUI (p-p)
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