參數(shù)資料
型號(hào): EP4SE530F43C3
廠商: Altera
文件頁(yè)數(shù): 62/82頁(yè)
文件大小: 0K
描述: IC STRATIX IV FPGA 530K 1760FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計(jì): 28033024
輸入/輸出數(shù): 1120
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–57
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–43 lists the DPA lock time specifications for Stratix IV ES devices.
Figure 1–4 shows the DPA lock time specifications with DPA PLL calibration enabled.
Table 1–43. DPA Lock Time Specifications—Stratix IV ES Devices Only (1), (2), (3)
Standard
Training Pattern
Number of Data
Transitions in
one repetition
of training
pattern
Number of
repetitions
per 256
data
transitions
Condition
Maximum
SPI-4
00000000001111111111
2
128
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Parallel Rapid
I/O
00001111
2
128
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
10010000
4
64
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Miscellaneous
10101010
8
32
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
01010101
8
32
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Notes to Table 1–43
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time applies to commercial, industrial, and military speed grades.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = Data rate (Mbps)/Deserialization factor.
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_dpa_locked
rx_reset
DPA Lock Time
256 data
transitions
96 slow
clock cycles
256 data
transitions
256 data
transitions
96 slow
clock cycles
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EP4SE530F43C3ES 功能描述:IC STRATIX IV E 530K 1760-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:STRATIX® IV E 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
EP4SE530F43C3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV E 21248 LABs 976 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE530F43C3NES 功能描述:IC STRATIX IV E 530K 1760-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:STRATIX® IV E 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
EP4SE530F43C4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix IV E 21248 LABs 976 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE530F43C4ES 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA