參數資料
型號: EP4SE530H35C3ES
廠商: Altera
文件頁數: 33/82頁
文件大小: 0K
描述: IC STRATIX IV E 530K 1152-HBGA
標準包裝: 3
系列: STRATIX® IV E
LAB/CLB數: 21248
邏輯元件/單元數: 531200
RAM 位總計: 28033024
輸入/輸出數: 744
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1152-BBGA 裸露焊盤
供應商設備封裝: 1152-HBGA(40x40)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–31
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
mode (14)
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
transceiver
block
400
400
400
ps
N
18
channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
transceiver
blocks
650
650
650
ps
CMU PLL0 and CMU PLL1
Supported data
range
600
11300
600
10312.5
600
8500
Mbps
CMU PLL lock time
from
pll_powerdown
de-assertion
100
100
100
s
ATX PLL (6G)
Supported Data
Range
/L = 1
4800-5400 and
6000-6500
4800-5400 and
6000-6500
4800-5400 and
6000-6500
Mbps
/L = 2
2400-2700 and
3000-3250
2400-2700 and
3000-3250
2400-2700 and
3000-3250
Mbps
/L = 4
1200-1350 and
1500-1625
1200-1350 and
1500-1625
1200-1350 and
1500-1625
Mbps
ATX PLL (10G)
Supported Data
Range
9900
11300
9900
10312.5
Mbps
Transceiver-FPGA Fabric Interface
Interface speed
(non-PMA Direct)
25
325
25
325
25
265.625
MHz
Interface speed
(PMA Direct)
50
325
50
325
50
325
MHz
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 7 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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