參數(shù)資料
型號: EP4SE530H40C3NES
廠商: Altera
文件頁數(shù): 28/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV E 530K 1517-HBGA
標準包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計: 28033024
輸入/輸出數(shù): 976
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1517-BBGA 裸露焊盤
供應商設備封裝: 1517-HBGA(42.5x42.5)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–26
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Rise/fall time
0.2
0.2
0.2
UI
Duty cycle
45
55
45
55
45
55
%
Peak-to-peak
differential input
voltage
200
1200
200
1200
200
1200
mV
On-chip termination
resistors
100
100
100
VICM
1200 ± 10%
mV
Transmitter REFCLK
Phase Noise
10 Hz
-50
-50
-50
100 Hz
-80
-80
-80
dBc/Hz
1 KHz
-110
-110
-110
dBc/Hz
10 KHz
-120
-120
-120
dBc/Hz
100 KHz
-120
-120
-120
dBc/Hz
1 MHz
-130
-130
-130
dBc/Hz
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
10 KHz to
20 MHz
——
3
3
3
ps
RREF
——
2000
± 1%
2000
± 1%
——
2000
± 1%
Transceiver Clocks
Calibration block
clock frequency
10
125
10
125
10
125
MHz
reconfig_clk
clock frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
——
2.5/
37.5
—50
2.5/
37.5
—50
MHz
fixedclk
clock
frequency
PCIe Receiver
Detect
125
125
125
MHz
Delta time between
reconfig_clks
——
2
2
2
ms
Transceiver block
minimum
(gxb_powerdown)
power-down pulse
width
——
1
1
1
s
Receiver
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Data rate (Single
width,
non-PMA Direct) (16)
600
3750
600
3750
600
3750
Mbps
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 2 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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