參數(shù)資料
型號(hào): EP4SE530H40I4
廠商: Altera
文件頁數(shù): 49/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 530K 1517HBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計(jì): 28033024
輸入/輸出數(shù): 976
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1517-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 1517-HBGA(42.5x42.5)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–45
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–31 lists the transceiver jitter specifications for protocols supported by
Stratix IV GT devices.
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 1 of 2)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
XLAUI/CAUI Transmit Jitter Generation (1), (3)
Total Jitter
Pattern = PRBS-31
VOD = 800 mV
REFCLK
= 644.53 MHz
4 (XLAUI)/
10 (CAUI) channels in
Basic ×1 mode
0.30
0.30
0.30
UI
Deterministic
Jitter
0.17
0.17
0.17
UI
XLAUI/CAUI Receiver Jitter Tolerance (1)
Total Jitter
tolerance
Pattern = PRBS-31
> 0.62
UI
Sinusoidal Jitter
tolerance
Jitter Frequency = 40 KHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
> 5
UI
Jitter Frequency
4MHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
> 0.05
UI
XFI Transmitter Jitter Generation (2), (3)
Total jitter at
10.3125 Gbps
Pattern =
PRBS-31
Vod = 800 mV
REFCLK =
644.53 MHz
10 channels in Basic ×1 mode
0.3
0.3
UI
OTL 4.10 (1), (3)
Total Jitter at
11.18 Gbps
Pattern = PRBS-31
VOD = 800 mV
REFCLK
= 698.75 MHz
0.30
0.30
0.30
UI
Deterministic
Jitter
0.17
0.17
0.17
UI
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