參數(shù)資料
型號: EP4SE820H35C3
廠商: Altera
文件頁數(shù): 54/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 820K 1152HBGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 32522
邏輯元件/單元數(shù): 813050
RAM 位總計: 34093056
輸入/輸出數(shù): 744
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1152-BBGA 裸露焊盤
供應商設備封裝: 1152-HBGA(40x40)
1–50
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
DSP Block Specifications
Table 1–35 lists the Stratix IV DSP block performance specifications.
Table 1–35. Block Performance Specifications for Stratix IV DSP Devices (1)
Mode
Resources
Used
Performance
Unit
Number of
Multipliers
–1 Industrial
and–2/–2×
Commercial/
Industrial
Speed Grade
–3
Commercial
Speed
Grade
–3
Industrial
Speed
Grade
–4
Commercial
Speed
Grade
–4
Industrial
Speed
Grade
9×9-bit multiplier (A, C, E, G) (2)
1
520
460
400
MHz
9×9-bit multiplier (B, D, F, H) (2)
1
520
460
400
MHz
12×12-bit multiplier (A, E) (3)
1
540
500
440
MHz
12×12-bit multiplier (B, D, F, H) (3)
1
540
500
440
430
MHz
18×18-bit multiplier
1
600
550
480
MHz
36×36-bit multiplier
1
480
440
380
MHz
18×18-bit multiply accumulator
4
490
440
380
MHz
18×18-bit multiply adder
4
510
470
410
400
MHz
18×18-bit multiply adder-signed full
precision
2
490
450
440
390
MHz
18×18-bit multiply adder with
loopback (4)
2
390
350
310
300
MHz
36-bit shift (32-bit data)
1
490
440
380
MHz
Double mode
1
480
440
380
370
MHz
Notes to Table 1–35:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) The DSP block implements eight independent 9b9b multiplies using A, B, C, D for the top DSP half block and E, F, G, H for the bottom DSP half block
multipliers.
(3) The DSP block implements six independent 12b12b multiplies using A, B, D for the top DSP half block and E, F, H for the bottom DSP half block
multipliers.
(4) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
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EP4SE820H35C3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE820H35C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE820H35C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE820H35I3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE820H35I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 32522 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256