參數資料
型號: EP4SGX180DF29C4
廠商: Altera
文件頁數: 8/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 180K 780FBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 3
系列: Stratix® IV GX
LAB/CLB數: 7030
邏輯元件/單元數: 175750
RAM 位總計: 13954048
輸入/輸出數: 372
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 780-BBGA
供應商設備封裝: 780-FBGA(29x29)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–8
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Bus Hold Specifications
Table 1–10 lists the Stratix IV device family bus hold specifications.
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 1–11 lists the Stratix IV OCT
termination calibration accuracy specifications.
Table 1–10. Bus Hold Parameters
Parameter
Symbol
Conditions
VCCIO
Unit
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Low
sustaining
current
ISUSL
VIN > VIL
(maximum)
22.5
25.0
30.0
50.0
70.0
A
High
sustaining
current
ISUSH
VIN < VIH
(minimum)
-22.5
-25.0
-30.0
-50.0
-70.0
A
Low
overdrive
current
IODL
0V < VIN <
VCCIO
120
160
200
300
500
A
High
overdrive
current
IODH
0V < VIN <
VCCIO
—-120—-160—-200—-300—-500
A
Bus-hold
trip point
VTRIP
0.450.950.501.000.681.070.70
1.70
0.802.00
V
Table 1–11. OCT Calibration Accuracy Specifications for Stratix IV Devices (Part 1 of 2) (1)
Symbol
Description
Conditions
Calibration Accuracy
Unit
C2
C3,I3, M3
C4,I4
25-
R
S
3.0, 2.5, 1.8, 1.5, 1.2
Internal series termination
with calibration (25-
setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
± 8
%
50-
R
S
3.0, 2.5, 1.8, 1.5, 1.2
Internal series termination
with calibration (50-
setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
± 8
%
50-
R
T
2.5, 1.8, 1.5, 1.2
Internal parallel termination
with calibration (50-
setting)
VCCIO = 2.5, 1.8, 1.5,
1.2 V
± 10
%
20-
, 40- , and
60-
R
S
3.0, 2.5, 1.8, 1.5, 1.2
Expanded range for internal
series termination with
calibration (20-
, 40-and
60-
R
S setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
± 10
%
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EP4SGX180DF29C4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180DF29I3 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180DF29I3N 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180DF29I4 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX180DF29I4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 7030 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256