參數(shù)資料
型號(hào): EP4SGX180KF40I3
廠商: Altera
文件頁數(shù): 71/82頁
文件大小: 0K
描述: IC STRATIX IV FPGA 180K 1517FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Stratix® IV GX
LAB/CLB數(shù): 7030
邏輯元件/單元數(shù): 175750
RAM 位總計(jì): 13954048
輸入/輸出數(shù): 744
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1517-BBGA
供應(yīng)商設(shè)備封裝: 1517-FBGA(40x40)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–65
Glossary
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
J
J
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing
Specifications
JTAG Timing Specifications:
K, L,
M, N, O
——
P
PLL
Specifications
Diagram of PLL Specifications (1)
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Q
——
RRL
Receiver differential input discrete resistor (external to Stratix IV device).
Table 1–54. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Core Clock
External Feedback
Reconfigurable in User Mode
Key
CLK
N
M
PFD
Switchover
VCO
CP
LF
CLKOUT Pins
GCLK
RCLK
fINPFD
fIN
fVCO
fOUT
fOUT_EXT
Counters
C0..C9
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EP4SGX180KF40I3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 7030 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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