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  • 參數(shù)資料
    型號(hào): EP4SGX290HF35I4
    廠商: Altera
    文件頁數(shù): 50/82頁
    文件大?。?/td> 0K
    描述: IC STRATIX IV FPGA 290K 1152FBGA
    產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
    標(biāo)準(zhǔn)包裝: 3
    系列: Stratix® IV GX
    LAB/CLB數(shù): 11648
    邏輯元件/單元數(shù): 291200
    RAM 位總計(jì): 17661952
    輸入/輸出數(shù): 564
    電源電壓: 0.87 V ~ 0.93 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 100°C
    封裝/外殼: 1152-BBGA
    供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
    1–46
    Chapter 1: DC and Switching Characteristics for Stratix IV Devices
    Switching Characteristics
    Stratix IV Device Handbook
    March 2014
    Altera Corporation
    Volume 4: Device Datasheet and Addendum
    Table 1–32 lists the SFI-S transmitter jitter specifications for Stratix IV GT devices.
    Sinusoidal Jitter
    tolerance
    Jitter Frequency = 40 KHz
    Pattern = PRBS-31
    Equalization = Disabled
    BER = 1E-12
    > 5
    UI
    Jitter Frequency
    4MHz
    Pattern = PRBS-31
    Equalization = Disabled
    BER = 1E-12
    > 0.05
    UI
    Notes to Table 1–31:
    (1) The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification.
    (2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1.
    (3) Contact Altera for board and link best practices at BER = 1E-15.
    Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)
    Symbol/
    Description
    Conditions
    –1 Industrial Speed
    Grade
    –2 Industrial Speed
    Grade
    –3 Industrial Speed
    Grade
    Unit
    Min
    Typ
    Max
    Min
    Typ
    Max
    Min
    Typ
    Max
    Table 1–32. SFI-S Transmitter Jitter Specifications for Stratix IV GT Devices (1), (2)
    Symbol/Description
    Conditions
    -1 Industrial
    Speed Grade
    -2 Industrial
    Speed Grade
    -3 Industrial
    Speed Grade
    Unit
    Mean
    Total Transmitter jitter at
    11.3 Gbps (4)
    Pattern = PRBS-31
    Vod = 800 mV
    REFCLK = 706.25 MHz
    12 channels in Basic ×1 mode
    0.23 UI (3)
    ——
    UI
    Notes to Table 1–32:
    (1) Dedicated refclk pins were used to drive the input reference clocks.
    (2) The jitter numbers are valid for stated conditions only.
    (3) Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units
    characterized was 0.30 UI.
    (4) Contact Altera for board and link best practices at BER = 1E-15.
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