- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4308 > EP4SGX290KF40C2N (Altera)IC STRATIX IV FPGA 290K 1517FBGA PDF資料下載
參數(shù)資料
| 型號： | EP4SGX290KF40C2N |
| 廠商： | Altera |
| 文件頁數(shù)： | 16/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV FPGA 290K 1517FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB數(shù)： | 11648 |
| 邏輯元件/單元數(shù)： | 291200 |
| RAM 位總計： | 17661952 |
| 輸入/輸出數(shù)： | 744 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1517-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1517-FBGA（40x40） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–15
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Power Consumption
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus II PowerPlay Power Analyzer feature.
1 You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Stratix IV core and periphery
blocks for commercial, industrial, and military grade devices.
The final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. There are no designations on finalized
tables.
BLVDS (8)
2.375 2.5
2.625 100
—
Notes to Table 1–22:
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–16.
(3) Differential clock inputs in column I/O are powered by VCC_CLKIN which requires 2.5 V. Differential inputs that are not on clock pins in column I/O are
powered by VCCPD which requires 2.5 V. All differential inputs in row I/O banks are powered by VCCPD which requires 2.5V.
(4) RL range: 90
RL 110 .
(5) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 1.0 V VIN 1.6 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is zero V VIN 1.85 V.
(6) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 0.85 V VIN 1.75 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is 0.45 V VIN 1.95 V.
(7) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins.
(8) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interfaces in Supported Altera Device
Table 1–22. Differential I/O Standard Specifications (1), (2) (Part 2 of 2)
I/O
Standard
VCCIO (V) (3)
VID (mV)
VICM(DC) (V)
VOD (V) (4)
VOCM (V) (4)
Min
Typ
Max
Min Condition Max
Min
Condition
Max
Min
Typ Max
Min
Typ
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACB90DHRT | CONN CARD EXTEND 180POS .050" |
| 24AA16HT-I/MS | IC EEPROM 16KBIT 400KHZ 8MSOP |
| EP4SE530F43I4 | IC STRATIX IV FPGA 530K 1760FBGA |
| 24AA16HT-I/ST | IC EEPROM 16KBIT 400KHZ 8TSSOP |
| EP4SE530F43C3 | IC STRATIX IV FPGA 530K 1760FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4SGX290KF40C3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX290KF40C3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX290KF40C4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX290KF40C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX290KF40I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。