參數(shù)資料
型號(hào)： EP4SGX360NF45I3N
廠商： Altera
文件頁(yè)數(shù)： 7/82頁(yè)
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 360K 1932FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 14144
邏輯元件/單元數(shù)： 353600
RAM 位總計(jì)： 23105536
輸入/輸出數(shù)： 920
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1932-BBGA
供應(yīng)商設(shè)備封裝： 1932-FBGA（45x45）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–7
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Handbook.
I/O Pin Leakage Current
Table 1–9 lists the Stratix IV I/O pin leakage current specifications.
VCCR_R
Receiver power (right side)
1.15
1.2
1.25
V
VCCT_L
Transmitter power (left side)
1.15
1.2
1.25
V
VCCT_R
Transmitter power (right side)
1.15
1.2
1.25
V
VCCL_GXBLn (3)
Transceiver clock power (left side)
1.15
1.2
1.25
V
VCCL_GXBRn (3)
Transceiver clock power (right side)
1.15
1.2
1.25
V
VCCH_GXBLn (3)
Transmitter output buffer power (left side)
1.33
1.4
1.47
V
VCCH_GXBRn (3)
Transmitter output buffer power (right side)
1.33
1.4
1.47
V
Notes to Table 1–8:
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(3) n = 0, 1, 2, or 3.
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 2 of 2) (1), (2)
Symbol
Description
Minimum
Typical
Maximum
Unit
Table 1–9. I/O Pin Leakage Current for Stratix IV Devices (1)
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0V to VCCIOMAX
-20
—
20
A
IOZ
Tri-stated I/O pin
VO = 0V to VCCIOMAX
-20
—
20
A
Note to Table 1–9:
(1) VREF current refers to the input pin leakage current.
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