參數(shù)資料
型號: EP4SGX530NF45C2
廠商: Altera
文件頁數(shù): 30/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 530K 1932FBGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 3
系列: Stratix® IV GX
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計: 28033024
輸入/輸出數(shù): 920
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1932-BBGA
供應商設備封裝: 1932-FBGA(45x45)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–28
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Differential on-chip
termination
resistors
85
setting
85 ± 20%
100
setting
100 ± 20%
120
setting
120 ± 20%
150-
setting
150 ± 20%
Differential and
common mode
return loss
PCIe (Gen 1
and Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
Serial RapidIO
SR/LR,
CPRI LV/HV,
OBSAI,
SATA
Compliant
Programmable PPM
detector (7)
——
± 62.5, 100, 125, 200,
250, 300, 500, 1000
ppm
Run length
200
200
200
UI
Programmable
equalization
——
16
16
16
dB
tLTR (8)
——
75
75
75
s
tLTR_LTD_Manual (9)
—15
15
15
s
tLTD_Manual (10)
4000
4000
4000
ns
tLTD_Auto (11)
4000
4000
4000
ns
Receiver buffer and
CDR offset
cancellation time
(per channel)
17000
17000
17000
reconfig_clk
cycles
Programmable DC
gain
DC Gain Setting
= 0
—0
0
0
dB
DC Gain Setting
= 1
—3
3
3
dB
DC Gain Setting
= 2
—6
6
6
dB
DC Gain Setting
= 3
—9
9
9
dB
DC Gain Setting
= 4
—12
12
12
dB
EyeQ Max Data Rate
4.0
4.0
4.0
Gbps
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 4 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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EP4SGX530NF45C2ES 制造商:Altera Corporation 功能描述:FPGA Stratix 制造商:Altera Corporation 功能描述:IC STRATIX IV FPGA
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