參數資料
型號: EP4SGX70HF35I3N
廠商: Altera
文件頁數: 47/82頁
文件大小: 0K
描述: IC STRATIX IV FPGA 70K 1152FBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 3
系列: Stratix® IV GX
LAB/CLB數: 2904
邏輯元件/單元數: 72600
RAM 位總計: 7564880
輸入/輸出數: 488
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應商設備封裝: 1152-FBGA(27x27)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–43
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
OBSAI Transmit Jitter Generation (19)
Total jitter at 768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT
0.35
0.35
0.35
UI
Deterministic jitter at
768 Mbps, 1536 Mbps,
and 3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT
0.17
0.17
0.17
UI
OBSAI Receiver Jitter Tolerance (19)
Deterministic jitter
tolerance at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.37
UI
Combined deterministic
and random jitter
tolerance at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.55
UI
Sinusoidal Jitter
tolerance at 768 Mbps
Jitter Frequency =
5.4 KHz
Pattern = CJPAT
> 8.5
UI
Jitter Frequency =
460 MHz to 20 MHz
Pattern = CJPAT
> 0.1
UI
Sinusoidal Jitter
tolerance at 1536 Mbps
Jitter Frequency =
10.9 KHz
Pattern = CJPAT
> 8.5
UI
Jitter Frequency =
921.6 MHz to 20 MHz
Pattern = CJPAT
> 0.1
UI
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1), (2) (Part 8 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
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