Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) DS507F2 EP7309 High-Performance, Low-Power S" />
參數(shù)資料
型號(hào): EP7309-CBZ
廠商: Cirrus Logic Inc
文件頁數(shù): 10/42頁
文件大?。?/td> 0K
描述: IC ARM720T MCU 74MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: EP7
核心處理器: ARM7
芯體尺寸: 32-位
速度: 74MHz
連通性: 編解碼器,DAI,EBI/EMI,IrDA,鍵盤,SPI/Microwire1,UART/USART
外圍設(shè)備: LCD,LED,MaverickKey,POR,PWM
輸入/輸出數(shù): 27
程序存儲(chǔ)器類型: ROMless
RAM 容量: 56K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 2.7 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-BGA
包裝: 托盤
其它名稱: 598-1211
18
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS507F2
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
EXPCLK
nCS
A
nM OE
HALF
WORD
D
nM W E
EXPRDY
WRITE
t
CSd
t
Ad
t
Ah
t
Ah
t
Ah
t
CSh
t
MOEh
t
MOEd
t
EXs
t
EXh
t
Ds
t
Dh
t
Ds
t
Ds
t
Ds
t
Dh
t
Dh
t
Dh
t
WRd
t
HW d
t
WDd
Figure 5. Static Memory Burst Read Cycle Timing Measurement
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