Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) DS506F2 EP7311 High-Performance, Low-Power S" />
參數(shù)資料
型號: EP7311-CB-90
廠商: Cirrus Logic Inc
文件頁數(shù): 8/42頁
文件大?。?/td> 0K
描述: IC ARM720T MCU 90MHZ 256-PBGA
標準包裝: 90
系列: EP7
核心處理器: ARM7
芯體尺寸: 32-位
速度: 90MHz
連通性: 編解碼器,EBI/EMI,IrDA,鍵盤,多媒體編解碼器,SPI/Microwire1,UART/USART
外圍設備: LCD,LED,MaverickKey,PWM
輸入/輸出數(shù): 27
程序存儲器類型: ROMless
RAM 容量: 56K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 2.7 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-BGA
包裝: 托盤
其它名稱: 598-1221
16
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS506F2
EP7311
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for
the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK rising edge to SDCS assert delay time
tCSa
024
ns
SDCLK rising edge to SDCS deassert delay time
tCSd
3
2
10
ns
SDCLK rising edge to SDRAS assert delay time
tRAa
137
ns
SDCLK rising edge to SDRAS deassert delay time
tRAd
3
1
10
ns
SDCLK rising edge to SDRAS invalid delay time
tRAnv
247
ns
SDCLK rising edge to SDCAS assert delay time
tCAa
22
5
ns
SDCLK rising edge to SDCAS deassert delay time
tCAd
50
3
ns
SDCLK rising edge to ADDR transition time
tADv
31
5
ns
SDCLK rising edge to ADDR invalid delay time
tADx
22
5
ns
SDCLK rising edge to SDMWE assert delay time
tMWa
31
5
ns
SDCLK rising edge to SDMWE deassert delay time
tMWd
40
4
ns
DATA transition to SDCLK rising edge time
tDAs
2-
-
ns
SDCLK rising edge to DATA transition hold time
tDAh
1-
-
ns
SDCLK rising edge to DATA transition delay time
tDAd
0
-
15
ns
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