Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) DS508F2 EP7312 High-Performance, Low-Power S" />
參數(shù)資料
型號(hào): EP7312-IB
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 10/54頁(yè)
文件大?。?/td> 0K
描述: IC ARM720T MCU 74MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: EP7
核心處理器: ARM7
芯體尺寸: 32-位
速度: 74MHz
連通性: 編解碼器,DAI,EBI/EMI,IrDA,鍵盤(pán),SPI/Microwire1,UART/USART
外圍設(shè)備: LCD,LED,MaverickKey,PWM
輸入/輸出數(shù): 27
程序存儲(chǔ)器類(lèi)型: ROMless
RAM 容量: 56K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 2.7 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-BGA
包裝: 托盤(pán)
配用: 598-1209-ND - KIT DEVELOPMENT EP73XX ARM7
其它名稱(chēng): 598-1240
18
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
ADRAS
ADCAS
SDCLK
SDCS
SDRAS
SDCAS
SDQM
[0:3]
ADDR
DATA
SDMWE
D1
D4
D3
D2
t
ADv
t
ADv
t
CSd
t
CSa
t
CSa
t
CAa
t
RAd
t
CSd
t
CAd
t
RAa
t
DAh
t
DAs
t
DAh
t
DAs
t
DAh
t
DAs
t
DAh
t
DAs
t
RAnv
Figure 4. SDRAM Burst Read Cycle Timing Measurement
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